Integrated circuits are widely used for consumer and commercial applications. One widely used class of integrated circuits are integrated circuit memory devices, including Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices.
Synchronous integrated circuit memory devices have been developed that can be synchronized with the clock speed of a processor. By using synchronous memory devices, the operational speed of a data processing system can be increased. Synchronous memory devices can include synchronous DRAMs (SDRAMs) or synchronous SRAMs (SSRAMs). The present application will be described with respect to an SDRAM. However, as will be described below, the present invention may be used with SSRAMS or other integrated circuits.
FIG. 1 is a block diagram of a conventional SDRAM device. As shown in FIG. 1, the SDRAM device 1 includes a memory cell array 10 that includes a plurality of bit lines, a plurality of word lines and a plurality of DRAM cells at intersections of the word lines and the bit lines. A row decoder circuit 14 selects the word lines in accordance with a row address from an address buffer circuit 12. A column decoder circuit 16 selects bit lines in response to a column address from the address buffer circuit 12.
Data stored in at least one DRAM cell at an intersection of at least one selected word line and at least one selected bit line, is sensed and amplified by a sense amplifier circuit 18. The sensed data is then transferred to a data output buffer circuit 22. In the SDRAM 1, a clock generating circuit 20 also is provided that generates a clock signal CLKDQ to clock the data output buffer circuit 22 in response to an externally applied clock signal XCLK at pad 2. Thus, the data output buffer circuit 22 outputs the data DQ1 through DQ2 to external of the SDRAM via output pads 3 in synchronization with the internal clock signal CLKDQ that is generated by the clock generating circuit 20. Although not shown in FIG. 1, the SDRAM also receives from external of the SDRAM, a row and column address XAi through XA1, data to be written, read/write commands and/or other data in synchronization with the external clock signal XCLK.
As the operating frequency of SDRAMs continues to increase, it may be desirable to provide clock generating circuits and methods that can operate at increasingly higher frequencies. For example, it may be desirable to generate the internal clock signal CLKDQ without the need for significant delay in the clock generating circuit 20. Thus, data may be output rapidly to external of the SDRAM.
FIG. 2 is a detailed circuit diagram of a clock generating circuit 20 of FIG. 1. Referring to FIG. 2, the clock generating circuit 20 includes a differential amplifier circuit 21, an internal buffer circuit 23, two inverters INV3 and INV4, a delay circuit 24, a NAND gate G1, a NOR gate G2 and an output driver circuit 25. Operation of the clock generating circuit 20 of FIG. 2 now will be described with reference to FIG. 3, which is a timing diagram that shows signal waveforms at various nodes of FIG. 2.
Referring to FIGS. 2 and 3, when the external clock signal XCLK remains low (that is, when a reference voltage VREF level is higher than the voltage level of the external clock signal XCLK), the output node N1 of the differential amplifier circuit 21 is at a logic high level. The node N2 transitions to a logic high level via the internal buffer circuit 23, so that the nodes N3, N4 and N5 transition to a logic low level, respectively. This enables the output (that is, the node N6) of the NOR gate G2 to transition to a logic low level. Accordingly, the clock signal CLKDQ from the clock generating circuit 20 remains low. In this example, a logic low level of the external clock signal XCLK having a TTL level may be about 0.4 volts, and a logic high level thereof may be about 2.4 volts. A logic low level of the external clock signal XCLK having a CMOS level may be about 0 volts, and a logic high level thereof may be about 3 volts. Alternatively, for CMOS, the logic high level may be more or less than 3 volts.
As illustrated in FIG. 3, when the external clock signal XCLK transitions from a logic low level to a logic high level, the output node N1 of the differential amplifier circuit 21 transitions to a logic low level. When the node N2 transitions from a logic high level to a logic low level via the internal buffer circuit 23, the node N6 (the output of the NOR gate G2) transitions to a logic high level because all of the inputs N2 and N5 of the NOR gate G2 become low. Therefore, a line 4 that transfers the clock signal CLKDQ to the data output buffer circuit 22 is driven high by means of the output driver circuit 25.
Then, as illustrated in FIG. 3, the node N5 has a low-to-high transition after a delay time that is determined by the inverter INV3 and the delay circuit 24. This forces the output N6 from the NOR gate G2 to transition to a logic low level regardless of the logic level of the other input of the NOR gate G2. Accordingly, the clock signal CLKDQ transitions from a logic high level to a logic low level. As illustrated in FIG. 3, the clock signal CLKDQ has a pulse width corresponding to the delay time t.sub.D which is determined by inverters INV3 and INV4, the delay circuit 24, and the gates G1 and G2.
At the high-to-low transition of the external clock signal XCLK, the nodes N1 and N2 transition to a logic high level and the nodes N3, N4, N5 turn to a logic low level as was described above. During subsequent clock cycles, the operation of the clock generating circuit 20 is identical to that described above.
The clock signal CLKDQ having a pulse width which corresponds to delay time t.sub.D automatically is generated whenever the external clock signal XCLK transitions from a logic low level to a logic high level. Unfortunately, the clock generating circuit 20 illustrated in FIG. 2 may not be desirable for high-speed synchronous memory devices (for example, SDRAM devices) because of the use of the internal buffer circuit 23. In particular, the time to generate the clock signal CLKDQ may be delayed relative to XCLK, by the delay of the internal buffer circuit 23, compared with the case where the internal buffer circuit 23 is not used.
However, if the internal buffer circuit 23 is not implemented in the clock generating circuit 20 in order to speed up the activation of the clock signal CLKDQ, the node N1 is directly connected to pull-up and pull-down transistors of the NOR gate G2. This may turn on the pull-up and pull-down transistors of the gate G2 due to the unstable level on the node N1 caused by the external clock signal XCLK. Stated differently, the voltage change slope on the node N1 may not be sharp, so that the current consumption of the NOR gate G2 may increase.
More specifically, the size of the respective elements of the differential amplifier circuit 21 may be reduced in order to reduce the current consumption. When the NOR gate G2 having a relatively large gate loading is directly biased by a voltage level on the node N1, the voltage from the NOR gate G2 may change less sharply. This may cause a delay in the activation of the clock signal CLKDQ. Therefore, in order to reduce the current consumption of the NOR gate G2 and to reduce the activation delay of the clock signal CLKDQ, the internal buffer circuit 23 generally is provided in the clock generating circuit 20 of a conventional synchronous memory device. The internal buffer circuit may add its own delay, as was described above.
Finally, the clock generating circuit 20 may be susceptible to noise, for example, ground line bounce. In particular, since the potential on the node N1 changes following the external clock signal XCLK, the level change slope of the node N1 may not be sharp. This may decrease the gate-to-source voltage of a pull-down transistor of the inverter INV1 during the low-to-high transition of the node N1. As a result, the clock generating circuit 20 may be susceptible to ground line bounce.